【討論】MOS驅(qū)動(dòng)芯片的設(shè)計(jì)考慮
怎樣根據(jù)MOS來(lái)選取合適的驅(qū)動(dòng)芯片，芯片技術(shù)指標(biāo)中那些與時(shí)間相關(guān)的參數(shù)到底有哪些影響，芯片內(nèi)部的功耗如何計(jì)算，為什么把芯片的輸入、或輸出通過(guò)耦合電容、驅(qū)動(dòng)變壓器后波形存在了各種各樣的問(wèn)題，各種功率拓?fù)涞降讘?yīng)該怎樣設(shè)計(jì)驅(qū)動(dòng)電路等.
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1。與時(shí)間相關(guān)的指標(biāo)
1。1 上升與下降時(shí)間
For the Rising time tr and Falling time tf are governed by three factors. These are operating temperature, supply voltage Vdd, and output load. Since the low side gate drivers were designed to drive power MOSFETs the output load is expressed in Farads. This is due to the fact that a MOSFET gate looks like a capacitor to the driving device, which is actually appears as a variable nonlinear capacitance. The rising time, tr, is defined as the period from 10% to 90% of output rail-to-rail level to supply source Vdd, while the falling time, tf, is defined as the period from 90% to 10% of output rail-to-rail level to supply source Vdd, both on Enable active, as shown in Fig. 1.
The rising and falling time is the function of output load Cload, supply voltage Vdd, and operating temperature. Little can be done to lower the rising and falling time except for keeping the device temperature low and choosing Cload as small as possible. There are several factors associated with the rising and falling times. In general, the rising and falling times are not equal creating a small asymmetry in the output waveform. This is due to having a P-channel device source current and an N-channel sink current from the load at the output stage. P-channels do not perform as well as N types, so this does not make the P equal to the N in dynamic performance. This difference is most obvious at higher loads. Meanwhile, rising and falling times also determine the minimum pulse width in that if an input pulse has a width that is less than the sum of the rising and falling times the output can’t make a full transition.
說(shuō)白了，上升與下降時(shí)間是針對(duì)輸出講的，也就是驅(qū)動(dòng)輸出10%-90%之間的時(shí)間延遲。
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@52football
1。與時(shí)間相關(guān)的指標(biāo)1。1上升與下降時(shí)間FortheRisingtimetrandFallingtimetfaregovernedbythreefactors.Theseareoperatingtemperature,supplyvoltageVdd,andoutputload.SincethelowsidegatedriversweredesignedtodrivepowerMOSFETstheoutputloadisexpressedinFarads.ThisisduetothefactthataMOSFETgatelookslikeacapacitortothedrivingdevice,whichisactuallyappearsasavariablenonlinearcapacitance.Therisingtime,tr,isdefinedastheperiodfrom10%to90%ofoutputrail-to-railleveltosupplysourceVdd,whilethefallingtime,tf,isdefinedastheperiodfrom90%to10%ofoutputrail-to-railleveltosupplysourceVdd,bothonEnableactive,asshowninFig.1.TherisingandfallingtimeisthefunctionofoutputloadCload,supplyvoltageVdd,andoperatingtemperature.LittlecanbedonetolowertherisingandfallingtimeexceptforkeepingthedevicetemperaturelowandchoosingCloadassmallaspossible.Thereareseveralfactorsassociatedwiththerisingandfallingtimes.Ingeneral,therisingandfallingtimesarenotequalcreatingasmallasymmetryintheoutputwaveform.ThisisduetohavingaP-channeldevicesourcecurrentandanN-channelsinkcurrentfromtheloadattheoutputstage.P-channelsdonotperformaswellasNtypes,sothisdoesnotmakethePequaltotheNindynamicperformance.Thisdifferenceismostobviousathigherloads.Meanwhile,risingandfallingtimesalsodeterminetheminimumpulsewidthinthatifaninputpulsehasawidththatislessthanthesumoftherisingandfallingtimestheoutputcan’tmakeafulltransition.說(shuō)白了，上升與下降時(shí)間是針對(duì)輸出講的，也就是驅(qū)動(dòng)輸出10%-90%之間的時(shí)間延遲。[圖片]
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那么，上升或下降時(shí)間過(guò)慢、或過(guò)快又有什么問(wèn)題？
如果過(guò)慢，比較明顯的直觀感覺(jué)是功率MOS的開(kāi)關(guān)損耗將變大；如果過(guò)快，可能導(dǎo)致共模傳導(dǎo)、或幅射EMI的問(wèn)題，但是可以在驅(qū)動(dòng)輸出與功率MOS串入驅(qū)動(dòng)電阻，實(shí)現(xiàn)開(kāi)關(guān)損耗與EMI性能之間的均衡。
同時(shí)，上升或下降時(shí)間也將影響輸入信號(hào)的有效最小脈寬，也就是說(shuō)過(guò)短的脈沖，驅(qū)動(dòng)芯片可能視作無(wú)效。
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1。2 輸入、輸出延遲時(shí)間
The propagation delay could be cataloged as turn-on and turn-off delay times. The turn-on propagation delay from input to output, td1, is defined as the period from input high to 10% of output rail-to-rail level to supply source Vdd, while The turn-off propagation delay from input to output, td2, is defined as the period from input low to 90% of output rail-to-rail level to supply source Vdd, both on Enable active, as shown in Fig. 1. On the other hand, the enable on propagation delay from enable signal to output, td3, is defined as the period from Enable high to 10% of output rail-to-rail level to supply source Vdd, while the enable off propagation delay from enable signal to output, td4, is defined as the period from Enable low to 90% of output rail-to-rail level to supply source Vdd, both on input active, as shown in Fig.2
The propagation delay time is the function of input signal amplitude Vin, supply voltage Vdd, and operating temperature. Little can be done to lower the delay except for keeping the device temperature low. Need to note that slow rising input signals can give the appearance of long delay times. This comes from the fact that the trip point of the input (about 1.5V) of Schmitt trigger in the driver can often be higher than the 10% point in the waveform.
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輸入、輸出的延遲指的是輸入信號(hào)有、或無(wú)時(shí)，輸出端對(duì)應(yīng)的延遲時(shí)間。有時(shí)驅(qū)動(dòng)芯片還有使能端，使能端的電平由高變低、或由低變高時(shí)，同樣會(huì)造成輸出驅(qū)動(dòng)信號(hào)的延遲。輸入、輸出的信號(hào)傳遞延遲除了跟芯片內(nèi)部設(shè)計(jì)相關(guān)以外，如果輸入信號(hào)的上升沿、或下降沿過(guò)于平緩，也會(huì)引起傳遞時(shí)間變長(zhǎng)。
可以把驅(qū)動(dòng)芯片看作一個(gè)信號(hào)傳輸線，延遲時(shí)間為零當(dāng)然最好。但是實(shí)際的芯片不可能做到延遲時(shí)間為零，因?yàn)樾酒锩嬗幸欢研盘?hào)處理電路。這個(gè)延遲時(shí)間較長(zhǎng)的壞處：閉環(huán)系統(tǒng)將存在延時(shí)，可能造成系統(tǒng)的不穩(wěn)定；如果兩個(gè)通道的驅(qū)動(dòng)信號(hào)有一定的時(shí)序要求，可能會(huì)造成時(shí)序控制的混亂（該沒(méi)的驅(qū)號(hào)可還有；該有的信號(hào)卻無(wú)）。比如原邊驅(qū)動(dòng)與副邊同步整流管一般要有延時(shí)，如果這個(gè)延時(shí)在某個(gè)時(shí)候失控了，就有可能造成炸管。
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